As is well known by those skilled in the art, a continuing goal in manufacturing and production of semiconductors is a reduction in size of components and circuits with the concurrent result of an increase in the number of circuits and/or circuit elements such as transistors, capacitors, etc., on a single semiconductor device. This relentless and successful reduction in size of the circuit elements has also required reduction in the size of the conductive lines connecting devices and circuits. However, as the conducting lines are designed to be smaller and smaller, the resistance of the interconnects increases. Further, as the number of dielectric layers increases, the capacitive coupling between lines on the same level and adjacent level increases.
In the past, aluminum was used as the metal interconnect lines and silicon oxide as the dielectric. However, newer manufacturing techniques now favor copper as the metal for interconnect lines and various low K materials (organic and inorganic) are favored as the dielectric material. Not surprisingly, these material changes have required changes in the processing methods. In particular, because of the difficulty of etching copper without also causing unacceptable damage to the dielectric material, the technique of forming the metal interconnect lines has experienced significant changes. Namely, whereas aluminum interconnects could be formed by depositing a layer of aluminum and then using photoresist, lithography, and etching to leave a desired pattern of aluminum lines, the formation of copper interconnect lines are typically formed by a process now commonly referred to as a Damascene process. The Damascene process is almost the reverse of etching, and simply stated a trench, canal or via is cut, etched or otherwise formed in the underlying dielectric and is then filled with metal (i.e., copper).
Unfortunately, although copper has the advantages discussed above, it readily diffuses into dielectric material used in the manufacture of semiconductor devices, and it diffuses especially easily into silicon dioxide. Diffusion of copper into the dielectric materials of a semiconductor deice can cause serious reliability problems including electrical shorts. Therefore, it is typical to form a barrier layer between the copper used for conductors and leads and the dielectric material of a semiconductor device. Typical barrier layers may be formed of Ta (tantalum), TaN (tantalum nitride), Ti (titanium), TiN (titanium nitride) and various combinations of these metals as well as other metal. The barrier layer is typically formed on the bottom and sidewalls of the trenches and vias of the copper interconnects to prevent the copper from diffusing into the surrounding silicon dioxide as other dielectric material. A layer of silicon nitride is then typically deposited as a cover layer over the complete structure including the conductor areas and the dielectric layer before another layer or level of dielectric structure is deposited.
Unfortunately, silicon nitride adheres poorly to copper and may peel away thereby creating poor interface properties including a path for copper to diffuse into the subsequent or cover layer of dielectric material. The same path may also allow moisture and contaminants to diffuse from outside into the copper so as to form porous copper oxide.
Various ones of the above-mentioned problems have been addressed by the prior art, but none of the known prior art provides a solution to all of the problems in the simple and elegant method provided by the present invention. For example, U.S. Pat. No. 5,380,546, entitled “Multilevel Metallization Process for Electronic Components” and issued to Krishnan, et al., teaches the use of tungsten as both a barrier layer and a capping layer, but does not teach the unique method of forming an alloy as taught by the present invention. U.S. Pat. No. 6,130,157, entitled “Method to Form an Encapsulation Layer Over Copper Interconnects” issued to Liu, et al., teaches the use of several metals as a barrier layer and “treats” a tungsten capping layer with a nitrogen plasma, but does not teach nickel as the capping layer or simply heating to form an alloy as taught by the method of the present invention. U.S. Pat. No. 6,261,950, entitled “Self-Aligned Metal Caps for Interlevel Metal Connections” issued to Tobben, et al., does not teach the use of a barrier layer and teaches a first embodiment that selectively deposits a capping layer, but does not teach forming an alloy. The '950 patent also teaches a second embodiment that does not selectively deposit a second metal but does include a heat treatment although at a greater temperature than the present invention. A paper by T. Saito, et al., in proceedings of the IITC in 2001 at pages 15-17 teaches a self aligned metal capping process for Copper damascene interconnect. A Tungsten capping layer is selectively formed on the Cu interconnect using the preferential deposition phenomenon of W-CVD assisted by pre and post treatment. This technology is applied to 0.2 μm bipolar-CMOS LSI with multilevel Cu interconnects, and then yield, reliability and operation speed are evaluated.